cy2xp41 crystal to lvpecl clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-48923 rev. *a revised june 12, 2008 features one lvpecl output pair external crystal frequency: 25.0 mhz selectable output frequency: 62.5 mhz or 75 mhz low rms phase jitter at 75 mhz, using 25 mhz crystal (1.5 mhz?10 mhz): 0.27 ps (typical) low rms phase jitter at 62.5 mhz, using 25 mhz crystal (1.5 mhz?10 mhz): 0.38 ps (typical) pb-free 8-pin tssop package supply voltage: 3.3v commercial temperature range functional description the cy2xp41 is a pll (phase locked loop) based high performance clock generator. it is optimized to generate high performance clock frequencies for dvd-r applications. it uses cypress?s low noise vco technology to achieve less than 1 ps typical rms phase jitter, t hat meets application jitter requirements. the cy2xp41 has a crystal oscillator interface input and one lvpecl output pair. logic block diagram xin xout external crystal crystal oscillator pll clk clk# fs [+] feedback
cy2xp41 document #: 001-48923 rev. *a page 2 of 8 pinouts figure 1. pin diagram - 8 pin tssop 3 1 2 45 6 7 8 vdd vss xout xin vdd clk clk# fs table 1. pin definitions - 8 pin tssop pin name type description 1, 8 vdd power 3.3v power supply. all supply current flows through pin 1 2 vss power ground 3, 4 xout, xin xtal output and input parallel resonant crystal interface 5 fs lvcmos/lvttl input frequency select input, see ?frequency table? on page 3 6,7 clk#, clk lvpecl output differential clock output [+] feedback
cy2xp41 document #: 001-48923 rev. *a page 3 of 8 frequency table input output frequency (mhz) input xtal frequency (mhz) fs 25 0 62.5 25 1 75.0 absolute maximum conditions parameter description condition min max unit v dd supply voltage ?0.5 4.4 v v in [1.] input voltage, dc relative to vss ?0.5 v dd + 0.5 v t s temperature, storage non functional ?65 150 c t j temperature, junction 135 c esd hbm esd protection (human body model) jedec std 22-a114-b 2000 v ul?94 flammability rating at 1/8 in. v?0 ja [2] thermal resistan ce, junction to ambient 0 m/s airflow 100 c/w 1 m/s airflow 91 2.5 m/s airflow 87 operating conditions parameter description min max unit v dd 3.3v supply voltage 3.135 3.465 v t a ambient temperature, commercial 0 70 c t pu power up time for all v dd to reach minimum specified voltage (ensure power ramps are monotonic) 0.05 500 ms electrical characteristics for input parameter description test conditions min typ max unit v il input low voltage ? ? 0.3*v dd v v ih input high voltage 0.7*v dd ?? v i il input low current fs = v ss ?50 ? ? a i ih input high current fs = v dd ??115a c in input capacitance 15 pf dc electrical characteri stics for power supplies parameter description min typ max unit i dd [3] power supply current with output terminated ? ? 180 ma note 1. the voltage on any input or io pin cannot exceed the power pin during power up. power supply sequencing is not required. 2. simulated using apache sentinel ti software. the board is deri ved from the jedec multilayer standard. it measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). the internal layers are 100% copper pla nes, while the top and bottom layers have 50% metallization. no vi as are included in the model. 3. i dd includes ~16 ma of current that is dissipat ed externally in the output termination resistors. [+] feedback
cy2xp41 document #: 001-48923 rev. *a page 4 of 8 dc electrical characteristics for lvpecl output parameter description min typ max unit v cm common-mode voltage (clk + clk#) / 2, defined in figure 5 on page 5, using figure 2 on page 5 circuit. 175 ? 2000 mv v pp differential peak output voltage, defined in figure 5 on page 5, using figure 2 on page 5 circuit. 350 780 850 mv crystal characteristics parameter description min typ max unit mode of oscillation fundamental f frequency ? 25 ? mhz esr equivalent series resistance ? ? 50 c l crystal load capacitance ? 10 ? pf c s shunt capacitance ? ? 7 pf dl crystal drive level ? ? 300 w ac characteristics parameter description test conditions min typ max unit f out output frequency 62.5 ? 75.0 mhz t r /t f output rise/fall time defined in figure 5 on page 5 ? 350 ? ps t jitter( ) rms phase jitter (random) 75 mhz, (1.5 mhz - 10 mhz filter), 3.3v ? 0.27 ? ps 62.5 mhz, (1.5 mhz - 10 mhz filter), 3.3v ? 0.38 ? ps t dc duty cycle defined in figure 4 on page 5 45 ? 55 % [+] feedback
cy2xp41 document #: 001-48923 rev. *a page 5 of 8 measurement definitions figure 2. output load ac test circuit figure 3. rms phase jitter figure 4. output duty cycle figure 5. output rise and fall time and peak-peak voltage swing measurement point clk clk# 3.3v z=50 z=50 3.3v 110 110 62 62 2pf 2pf noise power offset frequency 1.5mhz 10mhz phase noise phase noise mask 40db/decade 20db/decade rms jitter = v area under the masked phase noise plot clk t pw t period t dc = t pw t period clk# v pp t r t f 80% 20% clk clk# vss v cm [+] feedback
cy2xp41 document #: 001-48923 rev. *a page 6 of 8 application information power supply filtering techniques as in any high speed analog circuitry, noise at the power supply pins degrades performance. to achieve optimum jitter perfor- mance, good power supply isolation practices are advised. figure 6. shows a typical filtering scheme. since all of the current flows through pin 1, the resistance and inductance between this pin and the supply is minimized. a 0.01 or 0.1 f ceramic chip capacitor is also located close to this pin to provide a short and low impedance ac path to ground. a ~5 to 10 f tantalum capacitor is also located in the vicinity of this device. figure 6. power supply filtering termination for 3.3v lvpecl output clk and clk# are pull up drivers that generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources are used for functionality. matched impedance techniques are used to maximize operating frequency and minimize signal distortion. figure 2 on page 5 shows a termination scheme that is recommended as a guideline. other suitable clock layouts exist and it is recom- mended that the board designers simulate to guarantee compat- ibility across all printed circuit and process variations. cypress recommends the following ru and rd values: ru=110 and rd=62 . this is a 40 load, which is used to achieve the specified common mode and peak-to-peak voltage swing. for optimal signal integrity, 40 traces are recommended. crystal input interface the cy2xp41 is characterized with 10 pf parallel resonant crystals. the capacitor values shown in figure 7. are determined using a 25 mhz 10 pf parallel resonant crystal and are chosen to minimize the ppm error. cypress recommends the following c1 and c2 values: c1 = c2 = 6.8pf. figure 7. crystal input interface 3.3v 10 f 0.1 f v dd v dd 0.01 f (pin 1) (pin 8) xin xout external crystal c1 c2 [+] feedback
cy2xp41 document #: 001-48923 rev. *a page 7 of 8 package drawing and dimensions figure 8. 8-pin thin shrunk sm all outline package (4.40mm body) z8 ordering information part number package type product flow CY2XP41ZXC 8-pin tssop commercial, 0c to 70c CY2XP41ZXCt 8-pin tssop?tape and reel commercial, 0c to 70c 8 pin1id seating plane 1 bsc. bsc 0-8 plane gauge 2.90[0.114] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 6.50[0.256] 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] 3.10[0.122] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] 0.25[0.010] 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] dimensions in mm[inches] min. max. 51-85093-a [+] feedback
document #: 001-48923 rev. *a revised june 12, 2008 page 8 of 8 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2xp41 ? cypress semiconductor corporation, 2009. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document history page document title: cy2xp41 crystal to lvpecl clock generator document number: 001-48923 rev. ecn no. submission date orig. of change description of change ** 2669117 03/05/09 xht/cxq/ kvm new data sheet *a 2718433 06/12/09 wwz/hmt no change. s ubmit to ecn for product launch. [+] feedback
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